Many modern integrated circuits include several layers of conductive wiring (often termed "runners") which are surrounded and covered by dielectrics, illustratively formed from silicon dioxide. The presence of gates and field oxides, together with the conformal properties of deposited silicon dioxide, tend to make dielectrics very bumpy or uneven. The unevenness of dielectrics makes the formation of additional levels of reliable conductors difficult.
Consequently, it is desired to planarize or smooth dielectric layer prior to further processing such as pattern replication followed by conductor definition. One method for planarizing upper level dielectrics is chemical-mechanical polishing (CMP). CMP is becoming a popular technique for the planarization of interlevel dielectric layers due to the high degree of global planarity that CMP provides. During CMP processing, the wafer, having partially fabricated integrated circuits covered by a thick dielectric, is polished upon a polishing wheel. The resulting upper surface of the interlevel dielectric is highly planar and provides a suitable base or substrate upon which further processing, such as the formation of layers of conductors or metallization may be performed.
However, those concerned with the development of CMP techniques have found that it is difficult to determine when to stop the grinding or polishing of the dielectric. In typical present day applications, it is desired to leave around 0.8 microns of silicon dioxide over the highest conductor after polishing. Usually, the wafer is polished for an initial period of time. Then the wafer is removed from the polishing wheel and the thickness of the oxide is measured. If needed, further polishing is performed for an additional period of time (and, if needed, the process is repeated) until the desired thickness of silicon dioxide is achieved. The polishing rate of the silicon dioxide layer depends upon a large number of factors and the polishing rate is somewhat variable. This variability of the polishing rate complicates the problem of obtaining a layer having a consistent thickness of silicon dioxide on top of the conductor.